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sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 1 n low cost n two 12-bit dacs on a single chip n low power 40 mw (20mw/dac) n double-buffered inputs n 5v supply operation n voltage outputs, 4.5v range n midscale preset, zero volts out n guaranteed +0.5 lsb max inl n guaranteed +0.75 lsb max dnl n 2 mhz 4-quadrant multiplying bandwidth n separate reference inputs n 28Cpin soic and plastic dip p ackages n either 12 or 8 bit m p bus description the sp9502 is a low power, dual version of the popular sp9345, quad 12-bit digital-to-analog converter. it features 4.5v output swings when using 5 volt supplies. the converter is double- buffered for easy microprocessor interface. each 12-bit dac is independently addressable and both dacs may be simultaneously updated using a single transfer command. the output settling-time is specified at 4 m s. the sp9502 is available in 28Cpin soic and dip packages, specified over commercial temperature range. dac dac latch latch latch latch 8 msb's 4 lsb's ref in 1 ref in 2 ? + ? + vout1 vout2 a cs wr1 b1/b2 wr2 xfer clr control logic input registers dac registers data inputs sp9502 dual, 12Cbit, voltage output d/a converter signal processing excellence
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v dd - gnd ..................................................................... -0.3v,+6.0v v ss - gnd .................................................................... +0.3v, -6.0v v dd - v ss ...................................................................................................................... -0.3v, +12.0v v ref ..................................................................................... v ss , v dd d in ....................................................................................... v ss , v dd power dissipation plastic dip .......................................................................... 375mw (derate 7mw/ c above +70 c) small outline ...................................................................... 375mw (derate 7mw/?c above +70?c) specifications (typical at 25?c, t min t a t max ; v dd = +5v, v ss = -5v, v ref = +3v; cmos logic level digital inputs; specifications apply to all grades unless otherwise noted.) parameter min. typ. max. units conditions digital inputs logic levels v ih 2.4 volts v il 0.8 volts 4 quad, bipolar coding offset binary reference input voltage range +3 +4.5 volts note 5 input resistance 6 8.8 k w d in = 1877, code dependent analog output gain -k +0.5 +2.0 lsb v ref = 3v; note 3 -j +1.0 +4.0 lsb v ref = 3v; note 3 +1.0 +5.0 lsb v ref = 4.5v; note 3 initial offset bipolar +0.25 +3.0 lsb d in = 2,048 voltage range bipolar +3.0 +4.5 volts output current +5.0 ma v ref = 3v +0.5 ma v ref = 4.5v static performance resolution 12 bits integral linearity -k +0.25 +0.5 lsb v ref = 3v; note 3 -j +0.5 +1.0 lsb v ref = 3v; note 3 +0.5 +3.0 lsb v ref = 4.5v; note 3 differential linearity -k +0.25 +0.75 lsb -j +0.25 +1.0 lsb monotonicity guaranteed dynamic performance settling time small signal 0.5 m s to 0.012% full scale 4 m s to 0.012% slew rate 4 v/ m s multiplying bandwidth 2 mhz
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 3 0 code 4095 inle, dlne plots +0.25 lsb dnle -0.25 lsb +0.25 lsb inle -0.25 lsb specifications (continued) (typical at 25?c, t min t a t max ; v dd = +5v, v ss = -5v, v ref = +3v; cmos logic level digital inputs; specifications apply to all grades unless otherwise noted.) parameter min. typ. max. units conditions stability gain 15 ppm/?c t min to t max bipolar zero 15 ppm/?c t min to t max switching characteristics t ds data set up time 140 100 ns to rising edge of wr1, t dn data hold time 0 ns figure 4 t wr write pulse width 140 100 ns t xfer transfer pulse width 140 100 ns t wc total write command 280 200 ns power requirements note 5 v dd +5v, 3%; note 4, 5 Cj, Ck 4 6 ma v ss -5v, 3%; note 4, 5 Cj, Ck 4 6 ma power dissipation 40 mw environmental and mechanical operating temperature -j, -k 0 +70 c storage -60 +150 c package _n 28Cpin plastic dip _s 28Cpin soic notes: 1. integral linearity, for the sp9502 , is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. 2. differential linearity is the deviation of an output step from the theoretical value of 1 lsb for any two adjacent digital input codes. 3. 1 lsb = 2*v ref /4,096. 4. v ref = 0v. 5. the following power up sequence is recommended to avoid latch up: v ss (-5v), v dd (+5v), refin.
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 4 are forced to 1000 0000 0000 and the dac outputs will settle to ov. active low. pin 13 wr1 write input1 in conjunction with cs (pin 14), enables input register selection, and controls the transfer of data from the input bus to the input registers. active low. pin 14 cs chip select enables writing data to input registers and/or transferring data from input bus to dac registers. pin 15 v out1 voltage output from dac1. pin 16 db 11 data bit 11; most significant bit. pin 17 db 10 data bit 10. pin 18 db 9 data bit 9. pin 19 db 8 data bit 8. pin 20 db 7 data bit 7. pin 21 db 6 data bit 6. pin 22 db 5 data bit 5. pin 23 db 4 data bit 4. pin 24 db 3 data bit 3. pin 25 db 2 data bit 2. pin 26 db 1 data bit 1. pin 27 db 0 data bit 0; lsb pin 28 n.c. no connection. pinout 28Cpin soic & dip pin assignments pin 1 n.c. no connection. pin 2 v out 2 voltage output from dac2. pin 3 v ss C5v power supply input. pin 4 v dd +5v power supply input. pin 5 clr clear. gated with wr2 (pin 12). active low. clears both dac outputs to 0v. pin 6 ref in2 reference input for dac2. pin 7 gnd ground. pin 8 b1/b2 byte 1/byte 2 selects data input format. a logic 1 on pin 8 selects the 12C bit mode, and all 12 data bits are presented to the dac(s) unchanged; a logic 0 selects the 8Cbit mode, and the four lsbs are connected to the four msbs, allowing an 8Cbit msbCjustified interface. pin 9 a address for dac selection a logic 0 selects dac 1; a logic 1 selects dac 2. pin 10 ref in1 reference input for dac1. pin 11 xfer transfer. gated with wr2 (pin 12); loads all dac registers simultaneously. active low. pin 12 wr2 write input 2 in conjunction with xfer (pin 11), controls the transfer of data from the input registers to the dac registers. in conjunction with clr (pin 5), the dac registers n.c. v out2 v ss v dd clr ref in 2 gnd b1/b2 a ref in 1 xfer wr2 wr1 cs n.c. db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 v out1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sp9502
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 5 most significant bits (msbs), allowing an 8-bit msb-justified interface. all data inputs are enabled using the cs signal in both modes. the digital inputs are designed to be both ttl and 5v cmos compatible. in order to reduce the dac full scale output sensitivity to the large weighting of the msbs found in conventional r-2r resistor ladders, the 3 msbs are decoded into 8 equally weighted levels. this reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mis- matches in resistors and switches by the same amount. linearity errors and stability are both improved for the same reasons. each d/a con- verter is separated from the data bus by two reg- isters, each consisting of level-triggered latches, figure 1 . the first register (input register) is 12- bits wide. the input register is selected by the address input a 0 and a 1 and is enabled by the cs and wr1 signals. in the 8-bit mode, the enable signal to the 8 msbs is disabled by a logic low on b1/b2 to allow the 4 lsbs to be updated. the second register (dac register), accepts the de- coded 3 msbs plus the 9 lsbs. the two dac registers are updated simultaneously for both dacs using the xfer and wr2 signals. using the clr and wr2 signals or the power-on-reset, (enabled when the power is switched on) the dac registers are set to 1000 0000 0000 and the dac outputs will settle to 0v. using the control logic inputs, the user has full control of address decoding, chip enable, data transfer and clearing of the dacs. the control logic inputs are level triggered, and like the data inputs, are ttl and cmos compatible. the truth table ( table 2 ) shows the appropriate functions associated with the states of the control logic inputs. the dacs themselves are implemented with a precision thinCfilm resistor network and cmos transmission gate switches. each d/a converter is used to convert the 12-bit input from its dac register to a precision voltage. the bipolar voltage output of the sp9502 is created on-chip from the dac voltage output (v dac ) by using an operational amplifier and two feedback resistors connected as shown in figure 2 . this configuration produces a 4.5v bipolar output range with standard offset binary coding. (see table 1 ) theory of operation the sp9502 consists of five main functional blocks input data multiplexer, data registers, control logic,12-bit d/a converters, and two bipolar output voltage amplifiers. the input data multi- plexer is designed to interface to either 12- or 8-bit microprocessor data busses. the input data format is controlled by the b1/b2 signal a logic 1 selects the 12-bit mode, while a logic 0 selects the 8-bit mode. in the 12-bit mode the data is transferred to the input registers without changes in its format. in the 8-bit mode, the four least significant bits (lsbs) are connected to the four features the sp9502 is a low power, dual version of the popular sp9345, quad 12-bit digital-to-analog converter. this dual, voltage output, 12-bit digital-to-analog converter features 4.5v output swings when using 5 volt supplies. the input coding format used is standard offset binary. (refer to table 1 below.) the converter utilizes double-buffering on each of the 12 parallel digital inputs, for easy microprocessor interface. each 12-bit dac is independently addressable and both dacs may be simulta- neously updated using a single xfer command. the output settling-time is specified at 4 m s to full 12Cbit accuracy when driving a 5kohm, 50pf load combination. the sp9502 , dual 12-bit digital- to-analog converter is ideally suited for applica- tions such as ate, process controllers, robotics, and instrumentation. the sp9502 is available in 28Cpin plastic soic and plastic dip packages, specified over the commercial (0 c to +70 c) temperature range. table 1. offset binary coding input output msb lsb 1111 1111 1111 vref - 1 lsb 1111 1111 1110 vref - 2 lsb 1000 0000 0001 0 + 1 lsb 1000 0000 0000 0 0000 0000 0001 -vref + 1 lsb 0000 0000 0000 -vref 1 lsb = 2v ref 2 12
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 6 using the sp9502 with double-buffered inputs loading data to load a 12-bit word to the input register of each dac, using a 12-bit data bus, the sequence is as follows: 1) set xfer=1, b1/b2=1, clr=1, wr1=1, wr2=1, cs=1. 2) set a (the dac address) to the desired dac 0 = dac 1 ; 1 = dac 2 . 3) set d11 (msb) through d0 (lsb) to the desired digital input code. 4) load the word to the selected dac by cycling wr1 and cs through the following sequence: 1 0 1 5) repeat sequence for each input register. to load a 12-bit word to the input register of each dac, using an 8-bit data bus, the sequence is as follows: 1) set xfer=1, b1/b2=1, clr=1, wr1=1, wr2=1, cs=1. 2) set d11 through d4 to the 8 msbs of the desired digital input code. 3) load the 8 msbs of the digital word to the selected input register by cycling wr1 and cs through the 1 0 1 sequence. 4) reset b1/b2 from 1 0. 5) set d11 (msb) through d8 to the 4 lsbs of the digital input code. 6) load the 4 lsbs by cycling wr1 and cs through the 1 0 1 sequence. 7) repeat sequence for each input register transferring data to transfer the 12-bit words in the two input registers to the two dac registers: 1) set clr=1, cs=1, wr1=1. dac 3 to 7 decode & 5 bits 8?it latch 4-bit latch db11-db8 db7-db4 ref in ? + vout 44 44 4 mux 4 4 4 8 12 db3-db0 input register dac register latch 40k 40k figure 1. detailed block diagram (only one dac shown) 2) cycle wr2 and xfer through the 1 0 1 sequence. to set the outputs of the two dacs to 0v, cycle wr2 and clr through the 1 0 1 sequence, while keeping xfer=1. one latch, or no latches the latches that form the registers can be used in a semi- transparent mode, and a fully- transparent mode. in order to use the sp9502 in either mode the user must be interfaced to a 12-bit bus only (b1=1). the semiCtransparent mode is set up such that the first set of latches is transparent and the second set is used to latch the incoming data. data is latched into the second set rather than the first set, in order to minimize glitch energy induced from the data formatting. in this mode, wr1 and cs are tied low, and wr2 and xfer are used to strobe the data to the addressed dac. each dac is addressed using the address line a. after the appropriate dac has been selected and the data is settled at the digital inputs, bringing wr2 and xfer low will transfer the data to the addressed dac. the user should be sure to bring xfer and wr2 high again so that the next selected dac will not be overwritten by the last digital code. this mode of operation may be useful in applications where preloading of the input registers is not necessary; figure 3, top . a fully transparent mode is realized by tying wr1, cs, wr2, and xfer all low. in this mode, anything that is written on the 12-bit data bus will be passed directly to the selected dac. since both latches are not being used, the previous digital word will be overwritten by the new data as soon as the address changes. this may be useful should the user want to calibrate a circuit, by taking full scale or zero scale readings for both dacs; figure 3, bottom.
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 7 figure 2. transfer function zeroing dac outputs while keeping xfer pin high, the dac outputs can be set to zero volts two different ways. the first involves the clr and wr2 pins. in normal operation, the clr pin is tied high, thus, disabling the clear function. by cycling wr2 and clr through "1" "0""1" sequence, a digital code of 1000 0000 0000 is written to both dac registers, producing a half scale output or zero volts. the second utilizes the built in power-on-reset. using this feature, the sp9502 can be configured such that during power-up, the second register will be digitally zeroed, producing a zero volt output at both dac outputs. this is achieved by powering the unit up with xfer in a high state. thus, with no external circuitry, the sp9502 can be powered up with the analog outputs at a known, zero volt output level. temporarily forcing both dac outputs to ov set wr1=1, cs=1, wr2=0, xfer=0. the dac registers can be temporarily forced to 1000 0000 0000 by bringing the clr pin low. this will cause the dac outputs to 0v, while the clr pin remains low. when the clr pin is brought back high, the digital code at the dac registers will again appear at the dac's digital inputs, and the analog outputs will return to their previous values. v in ? + v out d v out = ? x v in d 2048 ( ) v dac =x v in d 4,096 v dac a cs wr1 b1/b2 wr2 xfer clr function 0 1 1 x x address dac 1 and load input register 0 0 1 x x address dac 1 and load 4 lsbs 1 1 1 x x address dac 2 and load input register 1 0 1 x x address dac 2 and load 4 lsbs x ** ** x 1 transfer data from input registers to dac registers x x x x 1 sets all dac output voltages to 0v x 1 1 x 0 0 temporarily force both dac output voltages to 0v, while clr is low x1xxxxx invalid state with any other control line active xx1xxxx invalid state with any other control line active x = dont care; ** = dont care; however, cs and wr1 = 1 will inhibit changes to the input registers. table 2. control logic truth table
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 8 h l h l h l clr xfer wr2 140ns, t h l h l h l wr2 cs wr1 140ns, t data transfer from input register to dac's loads input data to first set of latches wr xfer figure 4. timing figure 3. latch control options (top) semiCtransparent latch mode; (bottom) fullyCtransparent latch mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 n.c. v out2 v ss v dd clr ref in 2 gnd b1/b2 a ref in 1 xfer wr2 wr1 cs n.c. db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 v out1 sp9502 +5v ?v 12?it data bus v out2 v out1 +3v references gnd address decode & control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 n.c. v out2 v ss v dd clr ref in 2 gnd b1/b2 a ref in 1 xfer wr2 wr1 cs n.c. db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 v out1 sp9502 +5v ?v 12?it data bus v out2 v out1 +3v references gnd address decode & control dac strobe
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 9 d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e package: plastic dual?n?ine (narrow) dimensions (inches) minimum/maximum (mm) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) a2 b b1 c d e e1 l 24?in 0.115/0.195 (2.921/4.953) 0.014/0.023 (0.356/0.584) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.155/1.280 (29.33/32.51) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15? (0?15? 28?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.385/1.454 (35.17/36.90) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15? (0?15?
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 10 d eh package: plastic small outline (soic) dimensions (inches) minimum/maximum (mm) 14?in a a1 l b e a a1 b d e e h l 16?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 18?in 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 20?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.496/0.512 (12.60/13.00) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc)) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 24?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.599/0.614 (15.20/15.59) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 28?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.348/0.363 (8.83/9.22) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0?8? (0?8?
sp9502ds/02 sp9502 dual, 12-bit, voltage output d/a converter ? copyright 1999 sipex corporation 11 ordering information model .................................................................................. temperature range ....................................................................................... package monolithic 12-bit dual dac voltage output: SP9502JN ................................................................................ 0?c to +70?c ........................................................................ 28-pin, 0.3" plastic dip sp9502kn ............................................................................... 0?c to +70?c ........................................................................ 28-pin, 0.3" plastic dip sp9502js ................................................................................ 0?c to +70?c ................................................................................. 28Cpin, 0.3" soic sp9502ks ............................................................................... 0 c to +70 c ................................................................................ 28Cpin, 0.3" soic sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. corporation signal processing excellence sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com sales office 233 south hillview drive milpitas, ca 95035 tel: (978) 934-7500 fax: (978) 935-7600 far east: japan: nippon sipex corporation yahagi no. 2 building 3-5-3 uchikanda, chiyoda-ku tokyo 101 tel: 81.3.3256.0577 fax: 81.3.3256.0621 european sales offices: england: sipex corporation 2 linden house turk street alton hampshire gu34 ian england tel: 44-1420-549527 fax: 44-1420-542700 e-mail: mikeb@sipex.co.uk germany: sipex gmbh gautinger strasse 10 82319 starnberg tel: 49.81.51.89810 fax: 49.81.51.29598 e-mail: sipex-starnberg@t-online.de please consult the factory for pricing and availability on a tape-on-reel option.

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